1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a function of reducing a consumed current and, more particularly, to a semiconductor integrated circuit having a function of setting the operation frequency of one of a plurality of circuit blocks lower than in a normal operation mode, while the circuit block is not functioning.
2. Description of the Related Art
In general, there are two methods for reducing power consumed by an LSI (large scale integrated circuit): One is to use a power save mode for decreasing the operation frequency in, for example, a waiting state, and the other is to set the frequency of a clock signal of one of a plurality of circuit blocks lower than in a normal operation mode, while the circuit block is not functioning. According to the latter method, the power (f.times.C.times.V:f=frequency, C=load capacity, v=power supply voltage) consumed by an alternating current due to the charge and discharge of a load capacity of the circuit block, is reduced.
To increase the operation speed of an LSI such as a memory LSI, a technique of constantly pulling up a bit line connected to a memory cell and decreasing a signal amplitude of the bit line when data is read out from the memory cell is known. FIG. 1 shows a circuit arrangement of one column of a memory LSI using this technique. As shown in FIG. 1, a number of memory cells, e.g., SRAM cells MC are connected between paired bit lines BL and BL. A sense amplifier SA is also connected between these bit lines. P-channel MOS transistors TP for pulling up the bit lines are each connected between each of the bit lines and the node of each power supply Vcc. The-gates of the MOS transistors TP are connected to the node of a ground Vss and biased so that the MOS transistors are always in an on-state.
When data is read out from the memory LSI, one of the SRAM cells MC is selected in response to a signal from a corresponding word line (not shown). In each of the SRAM cells MC, an N-channel MOS transistor in one of two CMOS inverters (not shown) is turned on, based on data stored in the SRAM cell. If a certain SRAM cell MC is selected, a current flows into the node of the ground Vss through one of the bit lines, for example, a bit line BL connected to the N-channel MOS transistor which is in the on-state in the selected SRAM cell, and the potential of the bit line BL reaches a low level. In this case, a direct current flows between the power supply Vcc and ground Vss via the bit line BL, and the low level of the bit line BL changes to an intermediate level between Vcc and Vss, in other words, the signal amplitude of the bit line BL is decreased. Therefore, the time required for pulling the potential of the bit line BL up to the power supply potential Vcc by the P-channel MOS transistor TP, in transition to a readout operation of subsequent data, can be shortened, with the result that a short access cycle can be achieved, i.e., a high-speed operation can be performed.
In the memory LSI shown in FIG. 1, when data is read out, a difference in potential caused between the bit lines BL and BL is amplified by the sense amplifier SA to generate detection data. The operation cycle of the sense amplifier SA is controlled by a sense enabling signal SE. The consumed current of the sense amplifier SA changes in accordance with a variation in the frequency of the signal SE. The consumed current of the memory LSI can thus be reduced by lowering the frequency of the sense enabling signal SE. However, the direct current flowing between Vcc and Vss through the bit line is not decreased simply by lowering the operation frequency, as described above. Since the cycle of a word line drive signal is synchronized with the sense enabling signal SE, if the operation frequency is lowered, the cycle of variations in the word line drive signal is lengthened and so is a period of time during which the direct current is flowing. If the sense amplifier SA is of a current mirror type as shown, a large direct current is required in order to achieve the high-speed operation. However, as described above, the direct current is not lessened even though the operation frequency is lowered.
If the operation frequency of a circuit is set lower than in a normal operation mode while the circuit is not functioning, the alternating current can be reduced, and the direct current cannot be reduced.